- 09/2023: Presented FPGA-Based ECC Accelerator for IoT Devices at VDAT 2023
About Me
Hi, I’m Tapas Rout, a Ph.D. researcher at IIT Bhubaneswar specializing in AI hardware acceleration, VLSI design, and HW-SW co-design. My current research focuses on designing compute architectures that are both energy-efficient and scalable for deep learning workloads, targeting deployment across resource-constrained edge devices and high-performance computing (HPC) systems. A key part of my work involves making balanced trade-offs between power, performance, and area (PPA) based on the specific constraints of each platform.
Prior to my Ph.D., I’ve held engineering and management roles in the private sector, where I led and delivered projects of varying complexity. I also contributed to national R&D efforts at CSIR-CEERI, working on secure processor design, neural accelerators, and real-time AR/VR systems as part of the Integrated Circuits and Systems Group (ICSG) and the Intelligent Systems Group (ISG).
I was involved in multiple ASIC tapeouts at 28nm and 65nm process nodes (TSMC and UMC), gaining hands-on experience across the full RTL-to-GDSII flow—including RTL design, verification, synthesis, place-and-route, and physical sign-off—over different projects. That experience continues to influence how I approach hardware architecture and implementation challenges today. I primarily work with Verilog, SystemVerilog, UVM, and Python, and have experience with industry-standard EDA toolchains.
| Programming | Verilog, SystemVerilog, UVM, SystemC, Python, TCL, C++ |
| Embedded Boards | STM32 (M0/M4/M7/H7), ESP32, TI MSP430, Raspberry Pi 4, NVIDIA Jetson, Xilinx Virtex-7 |
| EDA Tools | Virtuoso, Calibre, Sentaurus TCAD, Design Compiler, Genus, Innovus, VCS, NCSIM, Vivado, MATLAB, Keil uVision |
| Technology Nodes | 28 nm (TSMC), 65 nm (TSMC, UMC), 90 nm (UMC), 180 nm (TSMC, SMIC, SCL) |
Education
-
Doctor of Philosophy 2025 – 2029IIT Bhubaneswar | Electronics & Communication EngineeringGPA: 8.2/10 -
Bachelor of Technology 2012 – 2016VSSUT Burla | Electronics & Communication EngineeringGPA: 7.6/10 Young Scientist Research ProgramThesis: Simulation-Based Analysis of Tunneling Field-Effect Transistors for Low-Power Logic ApplicationsKey Projects
- Fabrication and Characterization of Si–Ge Infrared Detectors via DC Magnetron Sputtering (Class 1K cleanroom)
- High-Throughput FPGA-Based Adaptive Filter Design Using LMS Algorithm for Noise Cancellation
- FPGA Implementation of a Spiking Neural Network for Real-Time Pattern Recognition
Experience
-
Research Fellow 2024 – 2029IIT Bhubaneswar Research and Entrepreneurship Park -
Project Associate 2022 – 2024Central Electronics Engineering Research InstituteSee Projects
- Hardware-Accelerated Encryption and Key Management for Trusted Execution Environments on RISC-V in Secure IoT Applications.
- Developed a pipeline for capturing acoustic signatures of real-world spaces and reproducing spatial audio for immersive AR/VR experiences.
- Designed an image processing pipeline for automated segmentation and restoration of damaged Rajasthani murals for AR/VR-based digital heritage projects.
-
Manager 2021 – 2022Pasupati Group -
Instrumentation Engineer 2017 – 2018Pragati Milk Products Private Limited